Advanced Logic-in memory (LiM) circuit designs will be employed to explore new ways of merging logic and memory. Coarse-grain LiM will be implemented in suitable platform (see below) using 1C-1T architecture at the BEOL of CMOS circuitry. Novel fine-grain LiM designs will be designed based on 1T FeFET combined with CMOS. To implement our fine-grained LiM designs,  our strategic choice is to use existing technology of 1T FeFET NVM arrays embedded in a an advanced 28 nm super low power FDSOI platform which is developed and made available as a service by external foundry. For this purpose, the consortium will develop the necessary PDK and will order MPW chips to the external foundry. This core task targets objective 2 and 4 (OBJ2 and OBJ4).