Optimized ferroelectric HfO2 layers in a 1T-1C architecture will be integrated with 130 nm CMOS in the back end of line (BEOL) using an advanced 200 mm pilot processing line to demonstrate suitability for eFeRAM solutions. Two different designs will be implemented: one involves 16 kbit arrays and the other involves novel LiM designs. Our strategic choice to employ 130 nm bulk CMOS instead of the more advanced 28 nm FDSOI takes advantage of already existing Memory Advanced Demonstrators (MAD) platform at CEA-LETI. It uses 130 nm CMOS for the validation of alternative NVM such OxRAM and STT-MRAM and therefore offers excellent and unrivalled opportunity for direct benchmarking with our FeRAMs. Furthermore, most of the current MCUs in the IoT market use 130 nm CMOS so our validation will be implemented in a realistic environment. Finally, the use of a readily available 130 nm CMOS platform optimizes resources in this project avoiding excessive development costs associated with more advanced technology nodes. This core task targets objective 3 and 4 (OBJ3 and OBJ4).